I. Field of the Invention
The invention relates to electronic devices. More specifically, the invention relates to electrostatic discharge (ESD) protection devices.
II. Background of the Invention
An electrostatic discharge (ESD) device is a circuit element able to detect an electrostatic event such as a high voltage or high current event (spike). When the ESD device detects a high voltage or current event, it turns on and acts as a short circuit for the transient voltage peak to dissipate its current to a ground plane or to another plane. In normal operation, the ESD device does nothing (it""s turned off). The ESD device is designed such that it will not turn on anywhere around the normal operation range of voltage such as 0 to 5 volts for a CMOS device.
Grounded gate NMOS devices operating in the snapback regime are commonly used as ESD protection devices. For these devices to be effective, special care is taken in their layout to spread out the ESD current uniformly across the width of the device. The common approach for doing this is to have the drain contacts of the grounded gate NMOS placed at large enough a space from the gate edge, such that the large resistance of the drain diffusion will prevent the current from crowding into any local regions near the high field gate/drain edge. This approach, however, generally does not work in the case of salicided process because of the very low resistance of the salicided drain.
One way to address this problem is to break the drain diffusion and introduce an N-Well between the drain contact region and the gate edge region. The higher resistance of the N-Well provides the necessary resistance to make the current flow path uniform to maintain a uniform current flow. However, the maximum current per unit of N-Well width that can flow through the N-Well is limited by the total number of carriers in the N-Well (approximately of the order of q*N*vsat where q is the electronic charge, N is the total sheet carrier concentration in the N-Well and vsat is the saturated velocity of electrons through the N-Well). As a result, for processes that have low N-Well concentration, this approach is not very effective, since the ESD current handling ability of the device is reduced due to the lower N-Well concentration. Often, in these cases, the device will fail at very low ESD stress voltages because of the inability of the N-Well to support the current. What is needed is a scheme that can provide high enough resistance in the current path to keep the current flow uniform, yet does not limit the current capability as severely as described above, so that the final ESD capability is dictated by the grounded gate transistor and not by the N-Well.
A method and a device are disclosed. One embodiment of a method includes introducing into an integrated circuit a device comprising a transistor including a drain of a first conductivity type and a first concentration in a well of a first conductivity type and a second concentration, a first region of the first conductivity type and first concentration in the well, and a second region of a second conductivity type in the well between the first region and the drain. The method also includes coupling the device to a pad. In the presence of a pre-determined current at the pad, the device biases a junction between the second region and the well toward current flow in the absence of a latch-up event.